Computers , " Abstract—This article presents a highly regular and scalable AES hardware architecture, suited for full-custom as well as for semi-custom design flows. Contrary to other publications, a complete architecture even including CBC mode that is scalable in terms of throughput and in terms of the used k Contrary to other publications, a complete architecture even including CBC mode that is scalable in terms of throughput and in terms of the used key size is described. Similarities of encryption and decryption are utilized to provide a high level of performance using only a relatively small area 10, gate equivalents for the standard configuration. This performance is reached by balancing the combinational paths of the design.

Author:Kebei Nikora
Language:English (Spanish)
Published (Last):1 February 2010
PDF File Size:1.83 Mb
ePub File Size:18.18 Mb
Price:Free* [*Free Regsitration Required]

Metrics details Abstract A new technique for combinational logic optimization is described. The technique is a two-step process. In the first step, the nonlinearity of a circuit—as measured by the number of nonlinear gates it contains—is reduced. The second step reduces the number of gates in the linear components of the already reduced circuit.

The technique can be applied to arbitrary combinational logic problems, and often yields improvements even after optimization by standard methods has been performed.

We also show that, in the second step, one is faced with an NP-hard problem, the Shortest Linear Program SLP problem, which is to minimize the number of linear operations necessary to compute a set of linear forms. In addition to showing that SLP is NP-hard, we show that a special case of the corresponding decision problem is Max SNP-complete, implying limits to its approximability.

Previous algorithms for minimizing the number of gates in linear components produced cancellation-free straight-line programs, i. The straight-line programs produced by our techniques are not always cancellation-free. We have experimentally verified that, for randomly chosen linear transformations, they are significantly smaller than the circuits produced by previous algorithms.

Download to read the full article text References [1] S. Arora, C. Lund, R. Motwani, M. Sudan, M. Szegedy, Proof verification and the hardness of approximation problems.


Logic Minimization Techniques with Applications to Cryptology

We found the S-Boxes consume much of the total AES circuit power and the power for an S-Box is mostly determined by the number of dynamic hazards. In this paper, we propose a low-power S-Box circuit architecture: a multi-stage PPRM architecture over composite fields. In this S-Box, i the signal arrival times of gates are as close as possible if the depths of the gates from the primary inputs are the same, and ii the hazard-transparent XOR gates are located after the other gates that may block the hazards. This process is experimental and the keywords may be updated as the learning algorithm improves. Download to read the full conference paper text References J. Daemen and V.


A Very Compact S-Box for AES

Encryption and decryption data paths are combined and all arithmetic components are reused. By introducing a new composite field, the S-Box structure is also optimized. An extremely small size of 5. It requires only 0. By making effective use of the SPN parallel feature, the throughput can be boosted up to 2.


An Optimized S-Box Circuit Architecture for Low Power AES Design



A More Compact AES


Related Articles