The product operates at a MSPS conversion rate, with outstanding dynamic performance over its full operating range. The ADC requires only a single 3. No external reference or driver components are required for many applications. A power-down function may be exercised to bring total consumption to 4.
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The product operates at a MSPS conversion rate, with outstanding dynamic performance over its full operating range. The ADC requires only a single 3. No external reference or driver components are required for many applications. A power-down function may be exercised to bring total consumption to 4. In power-down mode, the digital outputs are driven to a high impedance state.
B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P. Box , Norwood, MA , U. Analog Devices, Inc. Specifications subject to change without notice. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied.
Exposure to absolute maximum ratings for extended periods may affect device reliability. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection.
Although the AD features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. III Sample tested only. IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only. Step ? F to Ground. Analog Input for ADC Can be left open if operating in single-ended mode, but recommend connection to a 0. F capacitor and a 25? Digital Outputs of ADC. Digital output power supply. Equivalent Analog Input Circuit Figure 5. Equivalent Reference Input Circuit Figure 6. Harmonic Distortion vs. Encode Rate Figure Analog Power Dissipation vs. Encode Pulsewidth High Figure Temperature 0. Differential Nonlinearity REV. B —7— AD 2.
The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing to ease interfacing with 2. During power-down the outputs transition to a high impedance state. The time it takes to achieve optimal performance after disabling the powerdown mode is approximately 15 clock cycles. Care should be taken when loading the digital outputs of any high speed ADC. The signal is buffered and fed forward to an on-chip sample-and-hold circuit.
The ADC core architecture is a bit-per-stage pipeline type converter utilizing switch capacitor techniques. Each of the 5 MSB stages provides sufficient overlap and error correction to allow optimization of performance with respect to comparator accuracy.
The output staging block aligns the data, carries out the error correction and feeds the data to the eight output buffers. The AD includes an on-chip reference nominally 1. This makes the ADC easy to interface with and requires very few external components for operation. In normal operation, the internal reference is used by strapping Pins 2 and 3 of the AD together. The input range can be adjusted by varying the reference voltage applied to the AD The full-scale range of the ADC tracks reference voltage changes linearly.
Whether used or not, the internal reference Pin 2 should be bypassed with a 0. F capacitor to ground. Timing The AD provides latched data outputs with four pipeline delays. Data outputs are available one propagation delay tPD after the rising edge of the encode command Figure 1. Timing Diagram. The dynamic performance of the converter will degrade at encode rates below this sample rate.
It only requires a 3 V supply, an analog input and encode clock to test the AD The analog input to the board accepts a 1 V p-p signal centered at ground. J2 should be used for singleended input drive Jump E19—E Both J1 and J2 are terminated to 50? Each analog path is ac-coupled to an on-chip resistor divider which provides the required dc bias. Timing can be modified at E Care was taken on the chip to match clock line delays and maintain sharp clock logic transitions.
This ADC uses an on-chip sample-and-hold circuit which is essentially a mixer. The user is advised to give commensurate thought to the clock source. Analog Input The analog input to the ADC is fully differential and both inputs are internally biased. This allows the most flexible use of ac or dc and differential or single-ended input modes.
For peak performance the inputs are biased at 0. See the specification table for allowable common-mode range when dc coupling the input. The inputs are also buffered to reduce the load the user needs to drive. The importance of this increases with sampling rate and analog input frequency. The nominal input range is 1.
B AD Figure B —9— AD Figure B REV. B This datasheet has been downloaded from: www.
Azul Airlines vol AD9283
The model number is a specific version of a generic that can be purchased or sampled. Status Status indicates the current lifecycle of the product. This can be one of 4 stages: Pre-Release: The model has not been released to general production, but samples may be available. Production: The model is currently being produced, and generally available for purchase and sampling. Last Time Buy: The model has been scheduled for obsolescence, but may still be purchased for a limited time. Obsolete: The specific part is obsolete and no longer available.
AD9283 Analog Devices, AD9283 Datasheet
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